1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

MT4C1M16C3, MT4LC1M16C3

For the latest data sheet revisions, please refer to the Micron
Web site:

www.micron.com/datasheets

FPM DRAM

PIN ASSIGNMENT (Top View)

FEATURES

· JEDEC- and industry-standard x16 timing,

functions, pinouts, and packages

· High-performance, low-power CMOS silicon-gate

process

· Single power supply (+3.3V ±0.3V or 5V ±0.5V)
· All inputs, outputs and clocks are TTL-compatible
· Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#

(CBR) and HIDDEN

· Optional self refresh (S) for low-power data

retention

· BYTE WRITE and BYTE READ access cycles
· 1,024-cycle refresh (10 row, 10 column addresses)
· FAST-PAGE-MODE (FPM) access

OPTIONS

MARKING

· Voltage

3.3V

· Packages

Plastic SOJ (400 mil)

Plastic TSOP (400 mil)

· Timing

50ns access

-5

60ns access

-6

· Refresh Rates

Standard Refresh (16ms period)

None

Self Refresh (128ms period)

· Operating Temperature Range

Commercial (0

C to +70

None

Extended (-20

C to +80

Part Number Example:

MT4LC1M16C3DJ-5

NOTE

: 1. The third field distinguishes the low voltage offering:

LC designates V

= 3.3V and C designates V

= 5V.

2. Contact factory for availability.
3. Available only on MT4C1M16C3 (5V)

1 MEG x 16 FPM DRAM PART NUMBERS

PART NUMBER

SUPPLY PACKAGE REFRESH

MT4LC1M16C3DJ-6

3.3V

SOJ

Standard

MT4LC1M16C3DJ-6 S

3.3V

SOJ

Self

MT4LC1M16C3TG-6

3.3V

TSOP

Standard

MT4LC1M16C3TG-6 S

3.3V

TSOP

Self

MT4C1M16C3DJ-6

SOJ

Standard

MT4C1M16C3TG-6

TSOP

Standard

GENERAL DESCRIPTION

The 1 Meg x 16 DRAM is a randomly accessed, solid-

state memory containing 16,777,216 bits organized in
a x16 configuration. The 1 Meg x 16 DRAM has both
BYTE WRITE and WORD WRITE access cycles via two
CAS# pins (CASL# and CASH#). These function identi-
cally to a single CAS# on other DRAMs in that either
CASL# or CASH# will generate an internal CAS#.

The CAS# function and timing are determined by

the first CAS# (CASL# or CASH#) to transition LOW and

44/50-Pin TSOP

DQ0
DQ1
DQ2
DQ3

DQ4
DQ5
DQ6
DQ7

NC
NC

WE#

RAS#

NC
NC

A0
A1
A2
A3

1
2
3
4
5
6
7
8
9
10
11

15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42
41
40

36
35
34
33
32
31
30
29
28
27
26

DQ15
DQ14
DQ13
DQ12

DQ11
DQ10
DQ9
DQ8

NC
CASL#
CASH#
OE#

A9
A8
A7
A6
A5
A4

42-Pin SOJ

DQ0
DQ1
DQ2
DQ3

DQ4
DQ5
DQ6
DQ7

NC
NC

WE#

RAS#

NC
NC

A0
A1
A2
A3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

DQ15
DQ14
DQ13
DQ12

DQ11
DQ10
DQ9
DQ8

NC
CASL#
CASH#
OE#

A9
A8
A7
A6
A5
A4

NOTE: The # symbol indicates signal is active LOW.

KEY TIMING PARAMETERS

SPEED

RAC

CAC

-5

84ns

50ns

20ns

25ns

15ns

30ns

-6

110ns

60ns

35ns

30ns

15ns

40ns

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

the last CAS# to transition back HIGH. Use of only one
of the two results in a BYTE access cycle. CASL#
transitioning LOW selects an access cycle for the lower
byte (DQ0-DQ7), and CASH# transitioning LOW se-
lects an access cycle for the upper byte (DQ8-DQ15).

Each bit is uniquely addressed through the 20 ad-

dress bits during READ or WRITE cycles. These are
entered ten bits (A0-A9) at a time. RAS# is used to latch
the first ten bits and CAS# the latter ten bits. The CAS#
function is determined by the first CAS# (CASL# or
CASH#) to transition LOW and the last one to transition
back HIGH. The CAS# function also determines
whether the cycle will be a refresh cycle (RAS#-ONLY)
or an active cycle (READ, WRITE, or READ-WRITE) once
RAS# goes LOW.

The CASL# and CASH# inputs internally generate a

CAS# signal that functions identically to a single CAS#
input on other DRAMs. The key difference is that each
CAS# input (CASL# and CASH#) controls its corre-

GENERAL DESCRIPTION (continued)

sponding DQ tristate logic (in conjunction with OE#
and WE#). CASL# controls DQ0-DQ7 and CASH# con-
trols DQ8-DQ15. The two CAS# controls give the
1 Meg x 16 DRAM BYTE WRITE cycle capabilities.

A logic HIGH on WE# dictates read mode, while a

logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE#
or CAS, whichever occurs last. Taking WE# LOW will
initiate a WRITE cycle, selecting DQ0-DQ15. If WE#
goes LOW prior to CAS# going LOW, the output pin(s)
remain open (High-Z) until the next CAS# cycle. If WE#
goes LOW after CAS# goes LOW and data reaches the
output pins, data-out (Q) is activated and retains the
selected cell data as long as CAS# and OE# remain LOW
(regardless of WE# or RAS#). This late WE# pulse re-
sults in a READ-WRITE cycle.

The 16 data inputs and 16 data outputs are routed

through 16 pins using common I/O. Pin direction is
controlled by OE# and WE#.

CASL#

CAS#

RAS#

NO. 2 CLOCK

GENERATOR

REFRESH

CONTROLLER

NO. 1 CLOCK

GENERATOR

1,024 x 1,024 x 16

MEMORY

ARRAY

OE#

DQ0

DQ15

REFRESH

COUNTER

CASH#

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

1,024

1,024 x 16

SENSE AMPLIFIERS

I/O GATING

1,024

DATA-OUT

BUFFER

WE#

ROW-

ADDRESS

BUFFERS (10)

ROW

DECODER

COLUMN-

ADDRESS

BUFFER

DATA-IN BUFFER

COLUMN

DECODER

FUNCTIONAL BLOCK DIAGRAM

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

GENERAL DESCRIPTION (continued)

The MT4LC1M16C3 must be refreshed periodically

in order to retain stored data.

FAST PAGE MODE ACCESS

FAST-PAGE-MODE operations allow faster data op-

erations (READ, WRITE or READ-MODIFY-WRITE)
within a row-address-defined (A0-A9) page boundary.
The FAST-PAGE-MODE cycle is always initiated with a
row address strobed in by RAS#, followed by a column
address strobed in by CAS#. Additional columns may
be accessed by providing valid column addresses,
strobing CAS# and holding RAS# LOW, thus executing
faster memory cycles. Returning RAS# HIGH termi-
nates the FAST-PAGE-MODE operation.

Returning RAS# and CAS# HIGH terminates a

memory cycle and decreases chip current to a reduced
standbylevel. The chip is also preconditioned for the
next cycle during the RAS# HIGH time. Memory cell
data is retained in its correct state by maintaining power

and executing anyRAS# cycle (READ, WRITE) or RAS#
REFRESH cycle (RAS# ONLY, CBR or HIDDEN) so that
all 1,024 combinations of RAS# addresses (A0-A9) are
executed at least every 16ms (128ms on the "S" ver-
sion), regardless of sequence. The CBR REFRESH cycle
will also invoke the refresh counter and controller for
row-address control.

BYTE ACCESS CYCLE

The BYTE WRITEs and BYTE READs are determined

by the use of CASL# and CASH#. Enabling CASL# will
select a lower byte access (DQ0-DQ7), while enabling
CASH# will select an upper byte access (DQ0-DQ15).
Enabling both CASL# and CASH# selects a WORD
WRITE cycle.

The 1 Meg x 16 DRAM may be viewed as two 1 Meg x

8 DRAMs that have common input controls, with the
exception of the CAS# inputs. Figure 1 illustrates the
BYTE WRITE and WORD WRITE cycles. Figure 2 illus-
trates BYTE READ and WORD READ cycles.

Figure 1

WORD and BYTE WRITE Example

STORED

DATA

RAS#

CASL#

WE#

X = NOT EFFECTIVE (DON'T CARE)

ADDRESS 1

ADDRESS 0

WORD WRITE

LOWER BYTE WRITE

CASH#

INPUT

DATA

INPUT

DATA

INPUT

DATA

STORED

DATA

INPUT

DATA

STORED

DATA

STORED

DATA

UPPER BYTE
(DQ8-DQ15)

OF WORD

LOWER BYTE

(DQ0-DQ7)

OF WORD

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

STORED

DATA

RAS#

CASL#

WE#

Z = High-Z

ADDRESS 1

ADDRESS 0

WORD READ

LOWER BYTE READ

STORED

DATA

CASH#

OUTPUT

DATA

STORED

DATA

OUTPUT

DATA

OUTPUT

DATA

OUTPUT

DATA

STORED

DATA

UPPER BYTE
(DQ8-DQ15)

OF WORD

LOWER BYTE

(DQ0-DQ7)

OF WORD

Additionally, both bytes must always be of the same

mode of operation if both bytes are active. A CAS#
precharge must be satisfied prior to changing modes of
operation between the upper and lower bytes. For ex-
ample, an EARLY WRITE on one byte and a LATE WRITE
on the other byte are not allowed during the same cycle.
However, an EARLY WRITE on one byte and a LATE
WRITE on the other byte, after a CAS# precharge has
been satisfied, are permissible.

DRAM REFRESH

Preserve correct memory cell data by maintaining

power and executing any RAS# cycle (READ, WRITE) or
RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN)
so that all 1,024 combinations of RAS# addresses are
executed within

REF (MAX), regardless of sequence.

The CBR and EXTENDED and SELF REFRESH cycles
will invoke the internal refresh counter for automatic
RAS# addressing.

An optional self refresh mode is available on the "S"

version. The self refresh feature is initiated by per-
forming a CBR REFRESH cycle and holding RAS# LOW
for the specified

RASS. The "S" option allows the user

the choice of a fully static, low-power data retention
mode or a dynamic refresh mode at the extended re-
fresh period of 128ms, or 125µs per row, when using a
distributed CBR REFRESH. This refresh rate can be
applied during normal operation, as well as during a
standby or battery backup mode.

The self refresh mode is terminated by driving

RAS# HIGH for a minimum time of

RPS. This delay

allows for the completion of any internal refresh cycles
that may be in process at the time of the RAS# LOW-
to-HIGH transition. If the DRAM controller uses a dis-
tributed CBR refresh sequence, a burst refresh is not
required upon exiting self refresh. However, if the
DRAM controller utilizes a RAS#-ONLY or burst CBR
refresh sequence, all 1,024 rows must be refreshed us-
ing a minimum

RC refresh rate prior to resuming nor-

mal operation.

STANDBY

Returning RAS# and CAS# HIGH terminates a

memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.

Figure 2

WORD and BYTE READ Example

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1, 5, 6; notes can be found on page 9); V

(MIN)

(MAX)

3.3V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

MIN

MAX UNITS NOTES

SUPPLY VOLTAGE

3.6

4.5

5.5

INPUT HIGH VOLTAGE:
Valid Logic 1; All inputs, I/Os and any NC

5.5

2.4

+ 1

INPUT LOW VOLTAGE:
Valid Logic 0; All inputs, I/Os and any NC

-1.0

0.8

-0.5

0.8

INPUT LEAKAGE CURRENT:
Any input at V

(0V

+ 0.3V)

;

-2

µA

All other pins not under test = 0V

OUTPUT HIGH VOLTAGE:
I

OUT

= -2mA

2.4

OUTPUT LOW VOLTAGE:
I

OUT

= 2mA

0.4

OUTPUT LEAKAGE CURRENT:
Any output at V

OUT

[0V

OUT

(MAX)];

-5

µA

DQ is disabled and in High-Z state

ABSOLUTE MAXIMUM RATINGS*

Voltage on V

Pin Relative to V

3.3V ..................................................... -1V to +4.6V
5V ........................................................... -1V

+7V

Voltage on NC, Inputs or I/O Pins Relative to V

3.3V ..................................................... -1V to +5.5V
5V ........................................................... -1V

+7V

Operating Temperature

(commercial) ...................................... 0°C to +70°C

(extended "ET") ............................ -20°C to +80°C

Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ........................................................ 1W

*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

OPERATING CONDITIONS AND MAXIMUM LIMITS

(Notes: 1, 2, 3, 5, 6; notes can be found on page 9); V

(MIN)

(MAX)

PARAMETER/CONDITION

SYMBOL SPEED 3.3V

UNITS NOTES

STANDBY CURRENT: TTL

ALL

(RAS# = CAS# = V

)

STANDBY CURRENT: CMOS (non-"S" version only)

ALL

500

µA

(RAS# = CAS# = other inputs = V

- 0.2V)

STANDBY CURRENT: CMOS ("S" version only)

ALL

150

µA

(RAS# = CAS# = other inputs = V

- 0.2V)

OPERATING CURRENT: Random READ/WRITE

-5

180

190

Average power supply current

-6

170

180

(RAS#, CAS#, address cycling:

RC =

RC [MIN])

OPERATING CURRENT: FAST PAGE MODE

-5

110

120

Average power supply current

-6

110

(RAS# = V

, CAS#, address cycling:

PC =

PC [MIN])

REFRESH CURRENT: RAS#-ONLY

-5

180

190

Average power supply current

-6

170

180

(RAS# cycling, CAS# = V

RC =

RC [MIN])

REFRESH CURRENT: CBR

-5

180

Average power supply current

-6

170

180

4, 7

(RAS#, CAS#, address cycling:

RC =

RC [MIN])

REFRESH CURRENT: Extended ("S" version only)
Average power supply current: CAS# = 0.2V or CBR cycling;

ALL

300

µA

4, 7

RAS# =

RAS (MIN); WE# = V

- 0.2V; A0-A11, OE# and

= V

- 0.2V or 0.2V (D

may be left open)

REFRESH CURRENT: Self ("S" version only)
Average power supply current: CBR with RAS# z

ALL

300

µA

4, 7

RASS (MIN) and CAS# held LOW; WE# = V

- 0.2V;

A0-A11, OE# and D

= V

- 0.2V or 0.2V

may be left open)

CAPACITANCE

(Note: 2; notes can be found on page 9);

PARAMETER

SYMBOL MAX UNITS

Input Capacitance: Addresses

p F

Input Capacitance: RAS#, CASL#, CASH#, WE#, OE#

p F

Input/Output Capacitance: DQ

p F

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12; notes can be found on page 9); V

(MIN)

(MAX)

AC CHARACTERISTICS

-5

-6

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

Access time from column address

Column-address hold time (referenced to RAS#)

Column-address setup time

ASC

Row-address setup time

ASR

Column address to WE# delay time

AWD

Access time from CAS

CAC

Column-address hold time

CAH

CAS# pulse width

CAS

10,000

32, 35

CAS# LOW to "Don't Care" during Self Refresh

CHD

CAS# hold time (CBR Refresh)

CHR

4, 28

Last CAS# going LOW to first CAS# to return HIGH

CLCH

CAS# to output in Low-Z

CLZ

26, 29

CAS# precharge time

Access time from CAS# precharge

CPA

CAS# to RAS# precharge time

CRP

CAS# hold time

CSH

CAS# setup time (CBR Refresh)

CSR

4, 27

CAS# to WE# delay time

CWD

18, 27

WRITE command to CAS# lead time

CWL

23, 29

Data-in hold time

19, 29

Data-in setup time

19, 29

Output disable

17, 26, 29

Output enable

OE# hold time from WE# during

OEH

READ-MODIFY-WRITE cycle

Output buffer turn-off delay

OFF

11, 17, 23

OE# setup prior to RAS# during HIDDEN Refresh cycle

ORD

FAST-PAGE-MODE READ or WRITE cycle time

FAST-PAGE-MODE READ-WRITE cycle time

PRWC

Access time from RAS#

RAC

RAS# to column-address delay time

RAD

Row-address hold time

RAH

RAS# pulse width

RAS

10,000

RAS# pulse width (FAST PAGE MODE)

RASP

125,000

RAS# pulse width (Self Refresh)

RASS

100

µs

Random READ or WRITE cycle time

104

RAS# to CAS# delay time

RCD

14, 27

READ command hold time (referenced to CAS)

RCH

16, 28

READ command setup time

RCS

Refresh period (1,024 cycles)

REF

Refresh period (1,024 cycles) "S" version

REF

128

RAS# precharge time

RAS# to CAS# precharge time

RPC

RAS# precharge time (Self Refresh)

RPS

105

READ command hold time (referenced to RAS#)

RRH

RAS# hold time

RSH

READ-WRITE cycle time

RWC

116

140

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

NOTES

All voltages referenced to V

This parameter is sampled. V

= +3.3V or 5.0V;

f = 1 MHz.

is dependent on output loading. Specified

values are obtained with minimum cycle time
and the output open.

Enables on-chip refresh and address counters.

The minimum specifications are used only to
indicate cycle time at which proper operation
over the full temperature range (0°C

70°C)

for commercial and (-20°C

80°C) for

extended "ET" is ensured.

An initial pause of 100µs is required after power-
up, followed by eight RAS# refresh cycles (RAS#-
ONLY or CBR), before proper device operation is
ensured. The eight RAS# cycle wake-ups should
be repeated any time the

REF refresh require-

ment is exceeded.

AC characteristics assume

T = 5ns.

(MIN) and V

(MAX) are reference levels for

measuring timing of input signals. Transition
times are measured between V

and V

(or

between V

and V

In addition to meeting the transition rate
specification, all input signals must transit
between V

and V

(or between V

and V

) in a

monotonic manner.

10. If CAS# = V

, data output is High-Z.

11. If CAS# = V

, data output may contain data from

the last valid READ cycle.

12. Measured with a load equivalent to two TTL

gates, 100pF and V

= 0.8V and V

= 2V.

13. If CAS# is LOW at the falling edge of RAS#, Q will

be maintained from the previous cycle. To
initiate a new cycle and clear the Q buffer, CAS#
must be pulsed HIGH for

CP.

14. The

RCD (MAX) limit is no longer specified.

RCD

(MAX) was specified as a reference point only. If

RCD was greater than the specified

RCD (MAX)

limit, then access time was controlled exclusively
by

CAC (

RAC [MIN] no longer applied). With or

without the

RCD limit,

AA and

CAC must

always be met.

15. The

RAD (MAX) limit is no longer specified.

RAD

(MAX) was specified as a reference point only. If

RAD was greater than the specified

RAD (MAX)

limit, then access time was controlled exclusively
by

AA (

RAC and

CAC no longer applied). With or

without the

RAD (MAX) limit,

AA,

RAC, and

CAC must always be met.

16. Either

RCH or

RRH must be satisfied for a READ

cycle.

17.

OFF (MAX) defines the time at which the output

achieves the open circuit condition; it is not a
reference to V

or V

18.

WCS,

RWD,

AWD, and

CWD are restrictive

operating parameters in LATE WRITE and READ-
MODIFY-WRITE cycles only. If

WCS

(MIN), the cycle is an EARLY WRITE cycle and the
data out-put will remain an open circuit through-
out the entire cycle. If

RWD

RWD (MIN),

AWD

AWD (MIN) and

CWD

CWD (MIN),

the cycle is a READ WRITE and the data output
will contain data read from the selected cell. If
neither of the above conditions is met, the state
of Q (at access time and until CAS# or OE# goes
back to V

) is indeterminate. OE# held HIGH and

WE# taken LOW after CAS# goes LOW result in a
LATE WRITE (OE#-controlled) cycle.

19. These parameters are referenced to CAS# leading

edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.

20. During a READ cycle, if OE# is LOW then taken

HIGH before CAS# goes HIGH, Q goes open. If
OE# is tied permanently LOW, LATE WRITE and
READ-MODIFY-WRITE operations are not
permissible and should not be attempted.

21. A HIDDEN REFRESH may also be performed

after a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.

22. All other inputs at 0.2V or V

- 0.2V.

23. Column address changed once each cycle.
24. LATE WRITE and READ-MODIFY-WRITE cycles

must have both

OD and

OEH met (OE# HIGH

during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE
cycle. The DQs will provide the previously read
data if CAS# remains LOW and OE# is taken back
LOW after

OEH is met. If CAS# goes HIGH prior

to OE# going back LOW, the DQs will remain
open.

25. The DQs open during READ cycles once

OD or

OFF occur.

26. The 3ns minimum is a parameter guaranteed by

design.

27. The first CASx edge to transition LOW.
28. The last CASx edge to transition HIGH.
29. Output parameter (DQx) is referenced to

corresponding CAS# input; DQ0-DQ7 by CASL#
and DQ8-DQ15 by CASH#.

30. Last falling CASx edge to first rising CASx edge.
31. Last rising CASx edge to next cycle's last rising

CASx edge.

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

READ CYCLE

tRRH

tCLZ

tCAC

tRAC

tAA

VALID DATA

OPEN

tOFF

tRCH

ROW

tRCS

tASC

tRAH

tRAD

tAR

tCAH

tRCD

tCAS

tRSH

tCSH

tRP

tRC

tRAS

tCRP

tASR

ROW

OPEN

RAS#

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

tOD

tOE

OE#

V
V

IH
IL

COLUMN

WE#

CASL#/CASH#

tCLCH

DON'T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

CAC

CAH

CAS

10,000

CLCH

CLZ

CRP

CSH

OFF

RAC

RAD

RAH

RAS

10,000

104

RCD

RCH

RCS

RRH

RSH

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

DON'T CARE

UNDEFINED

V
V

IH
IL

VALID DATA

ROW

COLUMN

ROW

tDS

tWP

tWCH

tWCS

tWCR

tRWL

tCWL

tCAH

tASC

tRAH

tASR

tRAD

tAR

tCAS

tRSH

tCSH

tRCD

tCRP

tRAS

tRC

tRP

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

RAS#

OE#

tDH

tCLCH

WE#

CASL#/CASH#

EARLY WRITE CYCLE

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

CAH

CAS

10,000

CLCH

CRP

CSH

CWL

RAD

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

RAH

RAS

10,000

104

RCD

RSH

RWL

WCH

WCR

WCS

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

VALID D

OUT

VALID D

ROW

COLUMN

ROW

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

RAS#

OPEN

tOE

tOD

tCAC

tRAC

tAA

tCLZ

tDS

tDH

tAWD

tWP

tRWL

tCWL

tCWD

tRWD

tRCS

tASC

tCAH

tAR

tASR

tRAD

tCRP

tRCD

tCAS

tRSH

tCSH

tRAS

tRWC

tRP

tRAH

OE#

tOEH

tCLCH

WE#

CASL#/CASH#

DON'T CARE

UNDEFINED

READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

AWD

CAC

CAH

CAS

10,000

CLCH

CLZ

CRP

CSH

CWD

CWL

OEH

RAC

RAD

RAH

RAS

10,000

RCD

RCS

RSH

RWC

116

140

RWD

RWL

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

FAST-PAGE-MODE READ CYCLE

VALID

DATA

VALID

DATA

VALID

DATA

COLUMN

ROW

DON'T CARE

UNDEFINED

tRCS

tCAH

tASC

tCP

tRSH

tCP

tCAS,

tRCD

tCRP

tPC

tCSH

tRASP

tRP

tCAH

tASC

tCAH

tASC

tAR

tRAH

tRAD

tASR

tRCS

tRCH

tRCS

tRRH

tRCH

tOFF

tCAC

tCPA

tAA

tCLZ

tOFF

tCAC

tCPA

tAA

tCLZ

tOFF

tCAC

tRAC

tAA

tCLZ

tOE

tOD

tOE

tOD

tOE

tOD

OPEN

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

RAS#

OE#

tCLCH

tCAS, tCLCH

WE#

CASL#/CASH#

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

CAC

CAH

CAS

10,000

CLCH

CLZ

CPA

CRP

CSH

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

OFF

RAC

RAD

RAH

RASP

125,000

RCD

RCH

RCS

RRH

RSH

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

FAST-PAGE-MODE EARLY WRITE CYCLE

tDS

tDH

tDS

tDH

tDS

tDH

tWCR

VALID DATA

tRWL

tWP

tCWL
tWCH

tWCS

tWP

tCWL
tWCH

tWCS

tWP

tCWL
tWCH

tWCS

tCAH

tASC

tCAH

tASC

tCAH

tASC

tRAH

tASR

tRAD

tAR

COLUMN

ROW

tCP

tRSH

tCP

tRCD

tCRP

tPC

tCSH

tRASP

tRP

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

RAS#

OE#

tCAS, tCLCH

WE#

CASL#/CASH#

DON'T CARE

UNDEFINED

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

CAH

CAS

10,000

CLCH

CRP

CSH

CWL

RAD

RAH

RASP

125,000

RCD

RSH

RWL

WCH

WCR

WCS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

FAST-PAGE-MODE READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

DON'T CARE

UNDEFINED

tOD

tOE

tOD

tOE

tOD

tOE

OPEN

D OUT

VALID

D IN

VALID

D OUT

VALID

D IN

VALID

D OUT

VALID

D IN

VALID

OPEN

tDH

tDS

tAA

tCPA

tCLZ

tCAC

tDH

tDS

tAA

tCPA

tCLZ

tCAC

tDH

tDS

tAA

tCLZ

tCAC

tRAC

tWP

tCWL

tRWL

tCWD

tAWD

tWP

tCWL

tCWD

tAWD

tWP

tCWL

tCWD

tAWD

tRCS

tRWD

tASR

tRAH

tASC

tRAD

tAR

tCAH

tASC

tCAH

tASC

tCAH

tCP

tRSH

tCP

tRP

tRASP

tCP

tRCD

tCSH

tPC

NOTE 1

tCRP

ROW

COLUMN

ROW

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

RAS#

OE#

tPRWC

OEH

tCAS, tCLCH

WE#

CASL#/CASH#

NOTE: 1.

PC is for LATE WRITE only.

OEH

PRWC

RAC

RAD

RAH

RASP

125,000

RCD

RCS

RSH

RWD

RWL

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

AWD

CAC

CAH

CAS

10,000

CLCH

CLZ

CPA

CRP

CSH

CWD

CWL

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

NOTE: 1.

PC is for LATE WRITE only.

FAST-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

ROW

VALID

DATA

VALID DATA

OPEN

tCRP

tRCD

tCAS

tRSH

tRASP

tRP

tPC

tASC

tCAH

tAR

tASR

tRAD

tRAH

tWCS

tWP

tRWL

tRCS

tDH

tDS

tCAC

tOFF

V
V

IH
IL

CASL#/CASH#

V
V

IH
IL

ADDR

V
V

IH
IL

RAS#

V
V

OH
OL

WE#

V
V

IH
IL

tCSH

COLUMN

tCP

tASC

tCAH

tCWL

tWCH

tCLZ

tAA

RAC

DON'T CARE

UNDEFINED

NOTE 1

OE#

V
V

IH
IL

ROW

COLUMN

tCAS

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

CAC

CAH

CAS

10,000

CLZ

CRP

CSH

CWL

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

OFF

RAC

RAD

RAH

RASP

125,000

RCD

RCS

RSH

RWL

WCH

WCS

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

tRP

V
V

IH
IL

RAS#

tRAS

OPEN

tCHR

tCSR

V
V

IH
IL

CASL#/CASH#

tRP

tRAS

tRPC

tCSR

tRPC

tCHR

tCP

V
V

IH
IL

tWRP

tWRH

tWRP

tWRH

WE#

DON'T CARE

UNDEFINED

V
V

OH
OL

NOTE 1

RAS#-ONLY REFRESH CYCLE

(OE# and WE# = DON'T CARE)

ROW

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

RAS#

tRC

tRAS

tRP

tCRP

tASR

tRAH

ROW

OPEN

V
V

OH
OL

tRPC

CASL#/CASH#

CBR REFRESH CYCLE

(Addresses and OE# = DON'T CARE)

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASR

CHR

CRP

CSR

RAH

RAS

10,000

104

RPC

WRH

WRP

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTE: 1. End of CBR REFRESH cycle.

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

HIDDEN REFRESH CYCLE

(WE# = HIGH; OE# = LOW)

DON'T CARE

UNDEFINED

tCLZ

tOFF

OPEN

VALID DATA

OPEN

COLUMN

ROW

tCAC

tRAC

tAA

tCAH

tASC

tRAH

tASR

tRAD

tAR

tCRP

tRCD

tRSH

tRAS

tRP

tCHR

tRAS

DQx

V
V

IOH
IOL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

RAS#

tOE

tOD

CASL#/CASH#

V
V

IH
IL

OE#

ORD

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

CAC

CAH

CHR

CLZ

CRP

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

OFF

ORD

RAC

RAD

RAH

RAS

10,000

RCD

RSH

NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

SELF REFRESH CYCLE

(Addresses and OE# = DON'T CARE)

V
V

IH
IL

RAS#

tRASS

OPEN

V
V

IH
IL

V
V

OH
OL

tRPC

tCHD

tRPS

tRPC

tRP

tCP

CAS#

WE#

V
V

IH
IL

tWRH

tWRP

tWRH

tWRP

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

NOTE 1

tCSR

DON'T CARE

UNDEFINED

tCP

NOTE 2

(

)

(

)

(

)

(

)

NOTE: 1. Once

RASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.

2. Once

RPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used.

TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

CHD

CLCH

CSR

RASS

100

µs

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

RPC

RPS

105

WRH

WRP

1 Meg x 16 FPM DRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

D51_5V_B.p65 Rev. B; Pub 3/01

1 MEG x 16

FPM DRAM

44/50-PIN PLASTIC TSOP (400 mil)

NOTE:

1. All dimensions in inches (millimeters)

MAX

or typical where noted.

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per

side.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.

SEE DETAIL A

.024 (0.60)
.016 (0.40)

.008 (0.20)
.002 (0.05)

DETAIL A

.010 (0.25)

.032 (0.80)

TYP

.007 (0.18)
.005 (0.13)

.047 (1.20)

MAX

.004 (0.10)

.031 (0.80)

TYP

.018 (0.45)
.012 (0.30)

.828 (21.04)
.822 (20.88)

.467 (11.86)
.459 (11.66)

.402 (10.21)
.398 (10.11)

PIN #1 INDEX

SEATING PLANE

.029 (0.75) TYP

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT4C1M16C3

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT4C1M16C3